Explain 3 stage pipeline v/s 5 stage pipeline

Audience: Fresher to 2-3 years

Companies: startups working on RISCV, arm, intel

In last tutorial, we already saw some aspects of 3 stage pipelined processor. You can find it here

Let's explore, 5 stage pipeline today.

A pipeline is a processor design strategy that boosts a processor's overall performance and efficiency. It enables the processing of numerous instructions at once, each of which goes through a number of stages or phases. The 3-stage pipeline and the 5-stage pipeline are two popular pipeline designs.

In a 3-stage pipeline, the processing of each instruction is divided into three stages: fetch, decode, and execute. Each stage handles a specific operation, and multiple instructions can be in different stages of execution simultaneously.

The processing of instructions is further divided into five phases by a 5-stage pipeline: retrieve, decode, execute, memory access, and write back.
Fetch step: The fetch step involves retrieving the instruction from memory and updating the programme counter, much like the three-stage pipeline.
Decode Stage: The decode stage locates the operands, identifies the operation, and decodes the fetched instruction.
Execute Stage: During the execute stage, the computation and the instruction are carried out.
Memory Access Stage: The memory access stage is in charge of gaining access to memory so that data can be retrieved from or saved to memory. When it comes to load and store instructions, this stage is especially important.

Write Back Stage: The result of the performed instruction is written back to the relevant register or memory location during the write back stage.
The memory access and write back stages are added to the 3-stage pipeline in the 5-stage pipeline, enabling more effective memory operations and lowering inter-instruction dependencies.
Both the 3-stage and 5-stage pipelines boost instruction throughput by enabling the processing of many instructions at once. However, compared to the 3-stage pipeline, the 5-stage pipeline offers finer-grained control and more effective memory access, potentially improving performance. The actual performance benefit, however, may differ based on elements like instruction complexity, branch predictions, and memory access patterns.

When can we use 3 stage pipeline instead of 5 stage pipeline?

We always think that more the stages in pipeline better it is. But it brings us to a question. Is there a scenario where 3 stage pipeline is better than 5 stage one?

Simple Instruction Set: A 3-stage pipeline may be adequate if the processor primarily performs a small, straightforward instruction set with few dependents. For example, a simplified pipeline design can be more economical and simpler to implement in microcontrollers or embedded systems with modest processing needs.

Real-Time Systems: Minimising pipeline pauses and cutting overhead are essential for real-time systems since they frequently need predictable and deterministic execution. When compared to a more sophisticated pipeline design, a 3-stage pipeline can provide better predictability and lower latency.

Environments with strict Power Limitations: In battery-powered devices or systems with strict power limits, simplifying the pipeline can help save power. A 3-stage pipeline uses less electricity than a 5-stage pipeline because it needs fewer control registers and pipeline registers.

Interview question Bonus: What is the maximum stages of pipeline you have used in a processor. Based on your experience there can be questions on explain each stage of pipeline or name each stage. A real processor can easily have more than 10,11 stages. So don't bluff if you don't know the exact dyanmics.