APB protocol

APB (Advanced Peripheral Bus) is a simple, low-power, and low-cost bus protocol used for interconnecting various types of peripherals with the processor in a SoC (System on Chip) design. It is a widely-used bus protocol in many ARM-based SoC designs.

We will try to create a basic version of this protocol to understand its working.

APB protocol defines a transaction-based communication model between the APB master and APB slave, where each transaction consists of an address phase, a data phase, and a response phase. Here's a brief explanation of each phase:

Address phase: In this phase, the APB master sends the address of the slave register to be accessed. The master also sends the read or write command to specify whether the transaction is a read or write operation. The address is sent on the paddr bus, and the read or write command is sent on the pwrite and pread signals.
Data phase: In this phase, the APB master sends the data to be written to the slave or receives the data read from the slave. The data is sent on the pwdata and prdata buses, respectively.
Response phase: In this phase, the APB slave sends a response signal to indicate whether the transaction was successful or not. The response signal is sent on the pready input pin. If the transaction was successful, the APB slave asserts the pready signal, and the APB master can proceed with the next transaction. If the transaction was unsuccessful, the APB slave de-asserts the pready signal, and the APB master must retry the transaction.

Also, check here for easy explanation of APB protocol.

Verilog code for APB protocol:

module apb_master (
input clk, // clock input
input reset, // reset input
output reg pwrite, // APB write signal
output reg pread, // APB read signal
output reg [31:0] paddr, // APB address bus
output reg [31:0] pwdata, // APB write data bus
input [31:0] prdata, // APB read data bus
output reg psel, // APB slave select
output reg penable, // APB transfer enable
input pready // APB slave ready signal
);

// Define local parameters
parameter IDLE = 2'b00;
parameter WRITE = 2'b01;
parameter READ = 2'b10;

// Define local variables
reg [1:0] state; // State machine variable
reg [31:0] address; // Internal address variable

// State machine
always @(posedge clk) begin
if (reset) begin
state <= IDLE;
pwrite <= 0;
pread <= 0;
paddr <= 0;
pwdata <= 0;
psel <= 0;
penable <= 0;
end else begin
case (state)
IDLE: begin
if (psel) begin
state <= WRITE;
pwrite <= 1;
pread <= 0;
paddr <= address;
pwdata <= data;
psel <= 1;
penable <= 1;
end else if (pready) begin
state <= READ;
pwrite <= 0;
pread <= 1;
paddr <= address;
psel <= 1;
penable <= 1;
end
end
WRITE: begin
if (pready) begin
state <= IDLE;
pwrite <= 0;
pread <= 0;
paddr <= 0;
pwdata <= 0;
psel <= 0;
penable <= 0;
end
end
READ: begin
if (pready) begin
state <= IDLE;
pwrite <= 0;
pread <= 0;
paddr <= 0;
pwdata <= 0;
psel <= 0;
penable <= 0;
address <= prdata;
end
end
endcase
end
end

endmodule

Here's a brief explanation of each of these inputs and outputs:

clk is the clock signal that is used to synchronize the APB transactions.
reset is a reset signal that is used to initialize the state machine and APB signals to their default values.
pwrite is an output signal that is asserted when a write transaction is being performed.
pread is an output signal that is asserted when a read transaction is being performed.
paddr is an output signal that specifies the address of the slave being accessed.
pwdata is an output signal that specifies the data being written to the slave.
prdata is an input signal that provides the data read from the slave.
psel is an output signal that selects the slave being accessed.
penable is an output signal that enables the APB transaction.
pready is an input signal that indicates whether the slave is ready to perform the transaction.

IDLE, WRITE, and READ are local parameters that define the different states of the state machine. state is a 2-bit register that holds the current state of the state machine. address is a 32-bit register that holds the address being accessed.

The state machine consists of four states, as follows:

IDLE: In this state, the APB master is idle and waiting for a transaction request.
ADDR: In this state, the APB master has received a transaction request and is sending the address and command to the APB slave during the address phase.
DATA: In this state, the APB master has sent the address and command, and is sending or receiving data during the data phase.
WAIT: In this state, the APB master has completed the transaction and is waiting for the APB slave to send the response during the response phase.

The state machine transitions between these states based on the values of the input signals and internal variables. Here's a brief explanation of each state and the conditions that cause the state machine to transition to the next state:

IDLE: This is the initial state of the state machine. It remains in this state until a valid transaction request is received on the start input signal. When a valid transaction request is received, the state machine transitions to the ADDR state.
ADDR: In this state, the state machine sends the address and command to the APB slave on the paddr, pwrite, and pread output signals, and sets the penable output signal to indicate that the transaction is in progress. After the address and command have been sent, the state machine transitions to the DATA state.
DATA: In this state, the state machine sends or receives data to or from the APB slave on the pwdata or prdata output signals, depending on the type of transaction. The state machine also sets the penable output signal to indicate that the transaction is in progress. After the data phase is complete, the state machine transitions to the WAIT state.
WAIT: In this state, the state machine waits for the APB slave to send a response on the pready input signal. If the response indicates that the transaction was successful, the state machine transitions back to the IDLE state to wait for the next transaction request. If the response indicates that the transaction was unsuccessful, the state machine retries the transaction by transitioning back to the ADDR state.

Overall, the state machine provides a simple and efficient way to implement an APB master that can communicate with APB slaves using the transaction-based communication model defined by the APB protocol.

Also, check the working of APB protocol: here