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Your first program in Verilog without any tools installation

Expected time: Most users complete it in less than 1 hour.

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Getting started with a new language can be a very messy task. There can be a series of installations and plenty of things can go wrong. Also if you already work in a corporate setting then you might not want to do any installations and keep your personal practice separate. 

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Thankfully there is a very quick way to do that. 

So, let's get started. 

Step 1: Go to this URL: https://www.edaplayground.com).

If you are first time user, you might be asked to register, you can register using google and facebook. 

After successful login, you will be able to see something as below. 

 

 

 

 

 

 

 

 

 

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If you might need it, check troubleshooting tips at bottom of the page. 

Step 2: 

You can start writing your design and  testbench code straightaway. But to run your code you will need to save the code and select right tools at the left. First let's start writing the code.

Step 4: Define a Module

  • In the editor pane on the left side, begin by defining a module using the module keyword followed by the module name.

  • For example, let's create a simple module called myModule like below:

    • module myModule;​

Step 5: Declare Inputs and Outputs

  • Inside the module, declare the inputs and outputs using the input and output keywords, respectively. Each port declaration should include the data type and port name.

  • For this example, let's create a module with two inputs (in1 and in2) and one output (out), all of type wire:

    • module myModule(
        input wire in1,
        input wire in2,
        output wire out
      );

Step 6: Implement the Functionality

  • Inside the module, you can describe the functionality of your design using behavioral modeling constructs.

  • For this tutorial, let's create a simple AND gate that assigns the output out to the logical AND of inputs in1 and in2:

    • module myModule(
        input wire in1,
        input wire in2,
        output wire out
      );

    •   // AND gate implementation
        assign out = in1 & in2;

    • endmodule

  • If you don't understand the code yet, don't worry. This tutorial is just to give you the understanding of how tool works. 

Step 7: We have written the code now. Let's select the correct tool from the left side and save our program. You can save the program as public or private. For this tutorial, i have kept it public. 

Tools I have selected, design.sv and the output log when i run this program are as given below. 

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Screenshot 2023-06-01 11.50.55 AM.png
Screenshot 2023-06-01 12.07.23 PM.png
Screenshot 2023-06-01 12.07.14 PM.png
Screenshot 2023-06-01 12.07.32 PM.png

You must have already noticed the problem with this code. It is no fun as it does not display anything. It has no errors, but did it do anything? 

This is where verilog is different from other programming languages like C.  Here, we have decalared inputs and outputs in our module but we have not given any inputs and outputs. Like in the C program we have not said, where the main() function is. or where the program starts execution. 

No worries. We are not very far from doing that. We need a concept called testbench which we wll see in the coming tutorial. 

Meanwhile I have added the code of my program here : https://www.edaplayground.com/x/Gccr

Feel free to playaround and happy coding!!

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Disclaimer: This website does not endorse or claim ownership of external link edaplayground. It is a free tool which is used for tutorial purpose only. 

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Troubleshooting tip: edaplayground website is down sometimes and as a beginner it might be annoying if your log shows some weird errors and timeouts. It is not very usual and edaplayground is a very stable platform. But if such thing happens just visit the website in one or two days. 

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