Expected time: Most users complete it in less than 1 hour.

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In last tutorial, we saw how to write our first program without any tool. But it wasn't very cool as it didn't print anything useful. So today, we will add the testbench to verify the code we had written.  

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Step 1: Go to this URL: https://www.edaplayground.com). and open the program that we had written in the last tutorial. 

Step 2:Declare the Testbench Module

• Start by declaring the testbench module. It should have the same name as your Verilog module but with the suffix _tb.

• For example, if your Verilog module is myModule, the testbench module would be myModule_tb.

• Code : module myModule_tb;

Step 3: Declare Testbench Signals

• Declare signals to act as inputs and outputs for your testbench. These signals will drive the inputs of your DUT (Design Under Test) and capture the outputs.

• In this case, you need to declare signals for in1, in2, and out.

• Code: 

reg in1;
reg in2;
wire out;

Step 4: Instantiate the DUT

• Instantiate your DUT module within the testbench module. Connect the signals you declared in the previous step to the DUT ports.

• Code:

​myModule dut(
  .in1(in1),
  .in2(in2),
  .out(out)
);

Step 5: Provide Input Stimuli

• Use initial blocks to provide input stimuli to the DUT.

• Inside the initial block, assign values to the input signals (in1 and in2).

• Code:

initial begin
  in1 = 1'b0;
  in2 = 1'b1;

  // Add a delay to allow the inputs to settle
  #10;

  // Add additional test vectors here if needed

  // Terminate the simulation
  $finish;
end

Step 6: Display Output

• Use $display or $monitor statements to display or monitor the output of the DUT.

• Place the statement inside an always block to continuously display the value.

• Code:

​always @(out)
  $display("out = %b", out);

Step 7: Now as we have written the program, we also want to check in the waves how the inputs are changing over time. TO do so we will add following lines in our initial block. 

Code: 

    $dumpfile("dump.vcd");
    $dumpvars; 

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Check for the final code here: https://www.edaplayground.com/x/Gccr

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If you might need it, check troubleshooting tips at bottom of the page. 

Step 2: 

You can start writing your design and  testbench code straightaway. But to run your code you will need to save the code and select right tools at the left. First let's start writing the code.

Step 4: Define a Module

• In the editor pane on the left side, begin by defining a module using the module keyword followed by the module name.

• For example, let's create a simple module called myModule like below:

  • module myModule;​

Step 5: Declare Inputs and Outputs

• Inside the module, declare the inputs and outputs using the input and output keywords, respectively. Each port declaration should include the data type and port name.

• For this example, let's create a module with two inputs (in1 and in2) and one output (out), all of type wire:

  • module myModule(
      input wire in1,
      input wire in2,
      output wire out
    );

Step 6: Implement the Functionality

• Inside the module, you can describe the functionality of your design using behavioral modeling constructs.

• For this tutorial, let's create a simple AND gate that assigns the output out to the logical AND of inputs in1 and in2:

  • module myModule(
      input wire in1,
      input wire in2,
      output wire out
    );

  •   // AND gate implementation
      assign out = in1 & in2;

  • endmodule

• If you don't understand the code yet, don't worry. This tutorial is just to give you the understanding of how tool works. 

Step 7: We have written the code now. Let's select the correct tool from the left side and save our program. You can save the program as public or private. For this tutorial, i have kept it public. 

Tools I have selected, design.sv and the output log when i run this program are as given below. 

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