Inbuilt functions in verilog

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Verilog built-in functions, along with an example for each:

1. $clog2:

   • Description: Returns the minimum number of bits required to represent the logarithm base 2 of the input value.

   • Example: parameter WIDTH = $clog2(8); // WIDTH will be 3

2. $signed:

   • Description: Converts an expression to a signed value.

   • Example: reg [7:0] unsigned_value = 8'b10101010; reg signed [7:0] signed_value = $signed(unsigned_value);

3. $unsigned:

   • Description: Converts an expression to an unsigned value.

   • Example: reg signed [7:0] signed_value = -8; reg [7:0] unsigned_value = $unsigned(signed_value);

4. $random:

   • Description: Returns a random 32-bit value.

   • Example: reg [31:0] random_value = $random;

5. $display:

   • Description: Displays the specified string or values during simulation.

   • Example: $display("Value = %d", value);

6. $monitor:

   • Description: Monitors the specified variables and displays their values whenever they change.

   • Example: $monitor("Value changed: %d", value);

7. $time:

   • Description: Returns the current simulation time in simulation cycles.

   • Example: $display("Current time: %0t", $time);

8. $stime:

   • Description: Returns the simulation time as a string.

   • Example: $display("Simulation started at: %s", $stime);

9. $finish:

   • Description: Stops the simulation and ends the simulation run.

   • Example: if (condition) $finish;

10. $cast:

    • Description: Converts an expression to the specified data type.

    • Example: reg [7:0] data = $cast(reg [3:0], 5);`