UART protocol checker

Protocol: UART (Universal Asynchronous Receiver Transmitter)

1. Protocol Overview:

   • UART is a commonly used serial communication protocol.

   • It consists of a transmitter (TX) and a receiver (RX) that communicate using start bits, data bits, parity bits (optional), and stop bits.

   • The protocol defines specific timing requirements for each bit.

2. Protocol Checker Implementation:

   • Define a UVM component called uart_checker that inherits from uvm_component.

   • Implement the build_phase() function to configure the checker.

   • Create input/output ports for the TX and RX signals.

   • Inside the run_phase(), create a forever loop to continuously monitor the RX signal and check for protocol violations.

   • In the forever loop, wait for the start bit to be detected on the RX signal.

   • Once the start bit is detected, start monitoring the subsequent data and stop bits.

   • Check for violations such as incorrect data bits, missing or extra stop bits, or incorrect timing.

   • Report any violations using UVM's uvm_error or uvm_warning macros.

3. Example Checks:

   • Check for the correct number of data bits (e.g., 8 bits).

   • Verify the parity bit if it is used in the UART configuration.

   • Check for the correct number of stop bits (e.g., 1 or 2 bits).

   • Monitor the timing between bits to ensure they meet the protocol requirements.

   • Track the number of transmitted and received bytes to ensure they match.

4. Integration with Testbench:

   • Instantiate the uart_checker component in your testbench environment.

   • Connect the TX and RX signals of the DUT to the corresponding ports of the uart_checker.

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UVM code for the checker: 

`include "uvm_macros.svh"

class uart_checker extends uvm_component;
  // Input and output ports
  uvm_analysis_port #(bit) uart_rx;

  // Constructor
  function new(string name = "uart_checker", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  // UVM component macro
  `uvm_component_utils(uart_checker)

  // Build phase
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    uart_rx = new("uart_rx", this);
  endfunction

  // Run phase
  task run_phase(uvm_phase phase);
    bit rx_bit;
    forever begin
      uart_rx.get(rx_bit);
      if (rx_bit == 1'b0) begin
        // Start bit detected, start monitoring data and stop bits
        // Add your protocol checks here
      end
      // Add more checks and actions as per UART protocol
    end
  endtask
endclass

module tb;
  initial begin
    // Create and configure the UART checker
    uart_checker checker;
    checker = new("uart_checker");
    checker.uart_rx.connect(tb.uart_rx); // Connect the checker's RX port to DUT's RX signal

    // Start the simulation
    run_test();
  end

  // Your DUT signals
  wire uart_rx;
 
  // Test task
  task run_test();
    // Add test scenarios to stimulate the DUT
    // ...
  endtask
endmodule

This Testbench does not do a lot of things. But is just a minimal code to get us started. 

Now, we can add some additional checks for completeness of out checker. 

We will add following checks one-by-one in the coming tutorials. 

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1. Baud Rate Check: Verify that the duration of each bit, including start, data, and stop bits, aligns with the expected baud rate of the UART transmission. Check for timing violations that could indicate a mismatch in baud rate.

2. Framing Error Check: Detect framing errors by examining the transition between stop bit and the subsequent start bit. If the transition is not as expected (e.g., from high to low for start bit), it indicates a framing error.

3. Parity Error Check: If the UART communication uses parity, perform a parity error check. Validate the parity bit and compare it with the computed parity based on the received data bits. A mismatch indicates a parity error.

4. Break Condition Check: In UART, a break condition occurs when the line remains in the logic low state for a duration longer than a full word (start, data, and stop bits). Detect and flag the occurrence of a break condition.

5. Overrun Error Check: Monitor the RX signal to detect if new data arrives before the previous data is read. An overrun error occurs if the receiver fails to process the incoming data in time.

6. Data Validity Check: Verify that the received data bits adhere to the expected format, such as the number of data bits, the order of bits (LSB or MSB first), and any specified data encoding schemes.

7. Idle Line Check: Detect and report any violations of the idle line condition, which should be a continuous high state on the RX line when no data transmission is taking place.

8. Error Reporting: Capture and report any detected errors or violations in the UART communication, such as framing errors, parity errors, overrun errors, or break conditions. Utilize UVM's reporting features to display appropriate error messages.