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Watchdog Timer
The simplified version of Watchdog timer is quite similar to the binary counter that we had created.
Watchdog timers are frequently employed in microcontroller-based systems to monitor the execution of firmware or software. If the software hangs or stops responding, the watchdog timer will reset the system or trigger a recovery mechanism to prevent the system from remaining in an undesirable state.
Today, we will create a very simplified version of watchdog timer, which is as similar as generic timer.
Verilog code for the same is:
Complete code and results can be found at: https://edaplayground.com/x/LTpe
In this example, the WatchdogTimer module takes inputs such as clock (clk), reset (reset), and enable (enable), and provides an output signal (timeout) indicating whether a timeout has occurred.
The watchdog timer operates by incrementing a count register (count_reg) on every clock cycle when enabled. Once the count reaches a maximum value (COUNT_MAX), it resets back to zero and increments a timeout counter (timeout_counter). If the timeout counter reaches a predetermined timeout period (TIMEOUT_PERIOD), the timeout output is set to 1.
The module also handles the reset condition, where all the registers and counters are reset, and the timeout signal is set to 0.
Note that the values of COUNT_MAX and TIMEOUT_PERIOD can be adjusted based on the desired timeout duration and the clock frequency of your system.
In this testbench code, the WatchdogTimer_TB module is defined. It instantiates the WatchdogTimer module (dut) and connects the testbench signals (clk, reset, enable, and timeout) to the module under test.
The testbench includes a clock generation block that toggles the clock signal every 10 time units. It also provides a test stimulus in the initial block, where the reset signal is initially set to 1 for 10 time units, followed by enabling and disabling the watchdog timer at different intervals.
The simulation is run for a specific duration using delay statements (#). An assertion block is included to check if a timeout occurs, and it displays a message when the timeout signal (timeout) goes high.
Note that this is just a basic code and testbench, there is surely plenty of room for improvement, and please feel free to play around.
Code at: https://edaplayground.com/x/LTpe
Waveforms are given below: