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Wishbone protocol

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The Wishbone bus is a popular open-source hardware bus architecture used for interconnecting various modules within a digital system. The Wishbone bus protocol defines a standard interface for communication between different modules.

Let's understand the protocol with an example of two friends. 

1. Alisha wants to send a message to Ben. She prepares the message and needs to transmit it to Ben using the Wishbone protocol.

2. Alisha takes on the role of the master, and Ben takes on the role of the slave in this communication.

3. Alisha initiates the communication by asserting the `o_wb_cyc` (Cycle) and `o_wb_stb` (Strobe) signals. This indicates that a bus cycle is starting and that a transaction is about to take place.

4. Alisha sets the `o_wb_we` (Write Enable) signal to indicate that she wants to write data to the bus. This indicates that she intends to send a message to Ben.

5. Alisha sets the `o_wb_addr` (Address) signal to specify the location or destination where she wants to send the message, which is Ben's address.

6. Alisha puts the actual message in the `o_wb_data` (Data) signal. This is the content of the message she wants to send to Ben.

7. Alisha waits for Ben to receive and process the message.

8. Ben, acting as the slave, monitors the Wishbone bus for incoming transactions. When he detects the `o_wb_cyc` and `o_wb_stb` signals being asserted, he knows that Alisha wants to communicate with him.

9. Ben examines the `o_wb_we` signal and determines that it is a write operation, indicating that Alisha intends to send him a message.

10. Ben looks at the `o_wb_addr` signal and recognizes that the message is intended for him based on his address.

11. Ben reads the content of the message from the `o_wb_data` signal.

12. Once Ben has successfully received the message, he asserts the `i_wb_ack` (Acknowledge) signal to let Alisha know that he has received the message.

13. Alisha receives the `i_wb_ack` signal, indicating that Ben has received the message successfully.

14. If any errors occur during the transaction, such as data corruption or a failed transfer, Ben can assert the `i_wb_err` (Error) signal to indicate that the transaction encountered a problem.

15. Alisha can monitor the `i_wb_err` signal to detect if any errors occurred during the transmission.

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The Wishbone bus is a popular open-source hardware bus architecture used for interconnecting various modules within a digital system. The Wishbone bus protocol defines a standard interface for communication between different modules. The Wishbone bus supports various types of transactions, including:

  • 1. Single-cycle read (`STB`, `Cyc`, `WE`):
       - Initiates a single-cycle read transaction.
       - `STB` (Strobe) is asserted to indicate the start of the transaction.
       - `Cyc` (Cycle) indicates a single-cycle transaction.
       - `WE` (Write Enable) is deasserted to indicate a read operation.

  • 2. Single-cycle write (`STB`, `Cyc`, `WE`, `DAT`):
       - Initiates a single-cycle write transaction.
       - `STB` (Strobe) is asserted to indicate the start of the transaction.
       - `Cyc` (Cycle) indicates a single-cycle transaction.
       - `WE` (Write Enable) is asserted to indicate a write operation.
       - `DAT` (Data) carries the data to be written.

  • 3. Burst read (`STB`, `Cyc`, `WE`, `ADR`, `SEL`, `DAT`):
       - Initiates a burst read transaction.
       - `STB` (Strobe) is asserted to indicate the start of the transaction.
       - `Cyc` (Cycle) indicates a multi-cycle transaction.
       - `WE` (Write Enable) is deasserted to indicate a read operation.
       - `ADR` (Address) specifies the starting address of the burst.
       - `SEL` (Select) specifies the byte enables for byte-wide transfers.
       - `DAT` (Data) carries the read data.

  • 4. Burst write (`STB`, `Cyc`, `WE`, `ADR`, `SEL`, `DAT`):
       - Initiates a burst write transaction.
       - `STB` (Strobe) is asserted to indicate the start of the transaction.
       - `Cyc` (Cycle) indicates a multi-cycle transaction.
       - `WE` (Write Enable) is asserted to indicate a write operation.
       - `ADR` (Address) specifies the starting address of the burst.
       - `SEL` (Select) specifies the byte enables for byte-wide transfers.
       - `DAT` (Data) carries the write data.

  • These are some of the common transaction types supported by the Wishbone bus protocol. The specific transaction types and their details may vary depending on the implementation and version of the Wishbone specification used in a particular system.

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